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DATASHEET ADDENDUM
Intel 430HX PCIset
82439HX System Controller (TXC) Timing Specification
272945-001 September, 1996
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. The Intel 430HX PCIset Timing Specification Datasheet Addendum may contain design defects or errors known as errata. Current characterized errata are available on request. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725 (c)INTEL CORPORATION, 1996
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Intel 430HX PCIset 82439HX SYSTEM CONTROLLER (TXC) FEATURES
s Supports the Pentium(R) Processor at s Optional Parity s Optional Error Checking and
66 MHz, 60 MHz, and 50 MHz at 3 V
s Supports the Universal Serial Bus (USB) s Dual Processor Support
Correction (ECC) -- Superior DRAM Data Integrity -- Single-Bit Error Correction, Multi-Bit s PCI 2.1 Compliant Error Detection plus Nibble Failure Detection ECC Code s Integrated Second Level Cache -- Single- and Multi-bit Error Reporting Controller -- Virtual Swapable Bank Support (i.e., -- Direct Mapped Organization can swap out problem banks) -- Write-Back Cache Policy -- Merging Write Buffer Eliminates Most -- Cacheless, 256 Kbytes, and Partial Write Cycles 512 Kbytes s Fully Synchronous, Minimum Latency -- Pipelined Burst SRAMs 25/30/33 MHz PCI Bus Interface -- Cache Hit Read/Write Cycle Timings -- Zero Wait State CPU-to-PCI Write at 3-1-1-1 Timings for Superior Graphics -- Back-to-Back Read Cycles Performance at 3-1-1-1-1-1-1-1 -- Enhanced CPU-to-PCI Read Latencies -- Integrated Tag/Valid Status Bits for for Superior Graphics/PIO Cost Savings and Performance Performance -- Optional 512 MB DRAM Cacheability -- 21 DWORD PCI-DRAM Post Buffer Limit -- 22 DWord PCI-to-DRAM Read -- Supports 5 V SRAMs for Tag Address Prefetch Buffer s Integrated DRAM Controller -- Writeback Merging for PCI-to-DRAM -- 4 Mbytes to 512 Mbytes Memory Writes -- 64-Mbit DRAM Technology Support -- Writeback Forwarding for PCI-to-- Asymmetric DRAM Support DRAM Reads -- 8 Qword Deep Merging DRAM Write -- Pipelined Snoop Ahead Buffer -- Multi-Transaction Timer to Support -- Enhanced EDO/Hyper Page Mode Multiple Short PCI Transactions DRAM Supports 4-2-2-2 Reads and Within the Same PCI Arbitration Cycle x-2-2-2 Writes at 60 MHz, 5-2-2-2 s Single 324-Pin BGA Package Reads and x-2-2-2 Writes at 66 MHz -- 8 RAS Lines Available -- Integrated Programmable-Strength MA Buffers -- CAS-Before-RAS Refresh
REFERENCE INFORMATION: The information in this document is provided as a supplement to the standard package datasheet published for the Intel 430HX PCIset. Please refer to the standard package datasheet (order number 290551) for product information and specifications not found in this document. NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
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82439HX System Controller (TXC) Timing Specification
1.0 Electrical Characteristics .........................................................................................................................1 1.1 Absolute Maximum Ratings ................................................................................................................1 1.2 Thermal Characteristics ......................................................................................................................1 1.3 D.C. Characteristics ............................................................................................................................2 1.4 82439HX System Controller (TXC) AC Characteristics ......................................................................3 1.5 82439HX System Controller (TXC) Timing Diagrams .........................................................................8 FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. 82439HX System Controller (TXC) Package Thermal Resistance ............................................1 82439HX System Controller (TXC) D.C. Characteristics ...........................................................2 Host Clock Timing; 66 MHz (82439HX) .....................................................................................3 CPU Interface Timing; 66 MHz (82439HX) ................................................................................3 Second Level Cache Timing; 66 MHz (82439HX) .....................................................................5 DRAM Interface Timing; 66 MHz (82439HX) .............................................................................6 PCI Clock Timing; 66 MHz (82439HX) ......................................................................................6 PCI Interface Timing; 66 MHz (82439HX) ..................................................................................7 Clock Timing ..............................................................................................................................8 Propagation Delay .....................................................................................................................8 Valid Delay From Rising Clock Edge .........................................................................................8 Setup and Hold Times ...............................................................................................................9 Float Delay .................................................................................................................................9 Flow Through Delay ...................................................................................................................9 Pulse Width ..............................................................................................................................10 Output Enable Delay ................................................................................................................10
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1.0 1.1 Electrical Characteristics Absolute Maximum Ratings
82439HX (TXC) Timing Specification
Case Temperature under Bias .........................................................................................................0C to +85C Storage Temperature ................................................................................................................. -55C to +150C Voltage on Any Pin with Respect to Ground ...................................................................... -0.3 V to VDD + 0.3 V Maximum Power Dissipation ..................................................................................................................... 1.26 W WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operating beyond the "Operating Conditions" is not recommended and extended exposure beyond "Operating Conditions" may affect reliability.
1.2
Thermal Characteristics
The 82439HX is designed for operation at case temperatures between 0C and 85C. The thermal resistances of the 82439HX BGA (Ball Grid Array) package are given in Table 1. Table 1. 82439HX System Controller (TXC) Package Thermal Resistance Parameter Air Flow Meters/Second (Linear Feet per Minute) 0 (0) ja (C/Watt) (C/Watt)
jc
1.0 (196.9) 24.5
29.0 9.0
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82439HX (TXC) Timing Specification
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1.3
D.C. Characteristics
Table 2. 82439HX System Controller (TXC) D.C. Characteristics Functional Operating Range (VDD = 5V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C)
Symbol VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VOL1 VOH1 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IIH1 CIN COUT CI/O ICC
Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Current Output High Current Output Low Current Output High Current Input Leakage Current Input Capacitance Output Capacitance I/O Capacitance VCC Supply Current
Min -0.3 2.0 -0.3 2.0 -0.4 2.8 2.4
Max 0.8 VDD3 + 0.3 0.8 VDD + 0.3 0.8 VDD3 + 0.3 0.4 4
Unit V V V V V V V V mA mA mA mA mA mA A pF pF pF mA mA
Notes Notes 1,8; VDD3 = 3.135 V Notes 1,9; VDD3 = 3.6V Note 2; VDD = 4.75V Note 2; VDD = 5.25V Note 3; VDD3 = 3.135 Note 3; VDD3 = 3.6 Note 4 Note 4 Note 5 Note 5 Note 6 Note 6 Note 7 Note 7 0 V-2 8 -2 12 -2 10 10 10 10 10 350
NOTES: 1. VIL1 and VIH1 apply to the following 3.3 V input signals: A[31:3], BE[7:0]#, D/C#, W/R#, M/IO#, HLOCK#, ADS#, HITM#, CACHE#, SMIACT#, PHLD#, REQ[3:0]#, RST#, HCLKIN, PCLKIN as well the following signals when used as 3.3 V inputs during NAND tree testing: BRDY#, NA#, AHOLD, EADS#, BOFF#, KEN#/INV, CADV#, CADS#, CCS#, COE#, GWE#, BWE#, TWE#, MWE#, MA[11:2], MAA[1:0], MAB[1:0] 2. VIL2 and VIH2 apply to the following 5.0 V tolerant input signals: TIO[10:0], AD[31:0], C/BE[3:0]#, PLOCK#, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, PAR, SERR#, MD[63:0], MPD[7:0], HD[63:0] 3. VIL3 and VIH3 apply to the following input signals: TESTIN#, RST# 4. VOL1 and VOH1 apply to the following signals: TIO[10:0], TWE#, CADV#, CADS#, CCS#, COE#, GWE#, BWE#, A[31:3], HD[63:0], KEN#/INV, AHOLD, BRDY#, NA#, BOFF#, EADS#, MAA[1:0], MAB[1:0], MA[11:2], MWE#, MD[63:0], MPD[7:0], CAS[7:0]#, RAS[7:0]#, GNT[3:0]#, PHLDA#, AD[31:0], C/BE[3:0]#, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, PAR, SERR#, PLOCK# 5. IOL1 and I OH1 apply to: BRDY#, NA#, AHOLD, EADS#, BOFF#, KEN#/INV, CADV#, CADS#, CCS#, COE#, GWE#, BWE#, TWE#, A[31:3], T10[10:0], MD[63:0], MPD[7:0] 6. I OL2 and I OH2 apply to: MWE#, MA[11:2], MAA[1:0], MAB[1:0], RAS[7:0]#, CAS[7:0]#, PHLDA#, GNT[3:0]#, HD[63:0] 7. I OL3 and I OH3 apply to: MWE#, MA[11:2], MAA[1:0], MAB[1:0] if programmed for 12 mA strength 8. For transient voltages, VIL1 min is VSS - 1.4 V. This applies to the following signals: A[31:3], BE[7:0]#, D/C#, W/R#, M/IO#, HLOCK#, ADS#, HITM#, CACHE#. 9. For transient voltages, VIH1 max is VDD3 + 1.7 V. This applies to the following signals: A[31:3], BE[7:0]#, D/C#, W/R#, M/IO#, HLOCK#, ADS#, HITM#, CACHE#.
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1.4
All timings are in nanoseconds (ns), unless otherwise specified.
82439HX (TXC) Timing Specification
82439HX System Controller (TXC) AC Characteristics
Table 3. Host Clock Timing; 66 MHz (82439HX) Functional Operating Range (VDD = 5 V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C) Symbol t1 Parameter HCLKIN Period HCLKIN Period Stability t3 t4 t5 t6 HCLKIN High Time HCLKIN Low Time HCLKIN Rise Time HCLKIN Fall Time HCLKIN Rising Edge to PCLKIN Rising Edge Skew 1 6.0 6.0 1.2 1.2 6 66 MHz Min 15.0 Max 20.0 100 1 1 1 1 HCLKIN must lead PCLKIN Figures 1 pS Notes
Table 4. CPU Interface Timing; 66 MHz (82439HX) Functional Operating Range (VDD = 5V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C) (Sheet 1 of 2) Symbol t7 t7a t8 t9 t10 t11 t11a t12 t13 t14 Parameter ADS# Setup Time to HCLKIN Rising ADS# Hold Time from HCLKIN Rising W/R# Setup Time to HCLKIN Rising BE[7:0]# Setup Time to HCLKIN Rising HITM# Setup Time to HCLKIN Rising CACHE# Setup Time to HCLKIN Rising M/IO# Setup Time to HCLKIN Rising D/C# Setup Time to HCLKIN Rising HLOCK#, SMIACT# Setup Time to HCLKIN Rising HITM#, W/R#, M/IO#, D/C#, BE[7:0], HLOCK#, CACHE#, SMIACT# Hold Time from HCLKIN Rising A[31:3] Setup Time to HCLKIN Rising A[31:3] Hold Time from HCLKIN Rising A[31:3] Valid Delay from HCLKIN Rising 66 MHz Min 5.0 1.5 5.5 5.0 6.0 5.0 6.0 5.0 5.0 1.0 Max Figures 4 4 4 4 4 4 4 4 4 4 Notes
t15 t16 t18
3.0 1.0 2.0 13
4 4 3 0 pf 3
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82439HX (TXC) Timing Specification
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66 MHz Min 1.5 1.5 1.5 1.5 1.5 1.5 3.0 1.5 1.5 1.5 1.5 1.5 7.5 8.0 7.0 6.0 Max 8.0 8.0 7.0 7.0 7.0 7.0 Figures 3 3 3 3 3 3 4 4 3 3 3 3 0 pf 0 pf 0 pf 0 pf Notes 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf
Table 4. CPU Interface Timing; 66 MHz (82439HX) Functional Operating Range (VDD = 5V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C) (Sheet 2 of 2) Symbol t21 t22 t23 t24 t25 t26 t30 t31 t32 t33 t34 t35 Parameter BRDY# Valid Delay from HCLKIN Rising NA# Valid Delay from HCLKIN Rising AHOLD Valid Delay from HCLKIN Rising BOFF# Valid Delay from HCLKIN Rising EADS# Valid Delay from HCLKIN Rising KEN#/INV Valid Delay from HCLKIN Rising HD[63:0] Setup Time to HCLKIN Rising HD[63:0] Hold Time from HCLKIN Rising HD[63:0] Valid Delay from HCLKIN Rising HD[63:0] Valid Delay from HCLKIN Rising, 66 Mhz ECC enabled HD[63:0] Valid Delay from HCLKIN Rising, 60 Mhz 4 clk Leadoff, no L2 HD[63:0] Valid Delay from HCLKIN Rising, 66 MHz 5-222
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82439HX (TXC) Timing Specification
Table 5. Second Level Cache Timing; 66 MHz (82439HX) Functional Operating Range (VDD = 5V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C) Symbol Parameter 66 MHz Min Pipelined Burst SRAMs t40 t41 t42 t43 t44 t45 t45a t46 t47 t48 COE# Valid Delay from HCLKIN Rising TIO [10:0] Valid Delay from HCLKIN Rising TIO[10:0] Setup time to HCLKIN Rising TIO[10:0] Hold time from HCLKIN Rising TWE# Valid Delay from HCLKIN Rising GWE# Valid Delay from HCLKIN Rising BWE# Valid Delay from HCLKIN Rising CCS# Valid Delay from HCLKIN Rising CADS# Valid Delay from HCLKIN Rising CADV# Valid Delay from HCLKIN Rising 2.0 2.0 3.0 2.0 2.0 2.0 2.0 1.5 1.5 1.5 10.0 9.0 9.0 7.0 7.0 7.0 10.0 9.0 3 3 4 4 3 3 3 3 3 3 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf Max Figures Notes
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82439HX (TXC) Timing Specification
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Table 6. DRAM Interface Timing; 66 MHz (82439HX) Functional Operating Range (VDD = 5 V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C) Symbol t50 t51 t52 t53 t54 t55 t56 t57 t58 t59 t60 t61 t62 Parameter RAS[4:0]# Valid Delay from HCLKIN Rising CAS[7:0]# Valid Delay from HCLKIN Rising MWE# Valid Delay from HCLKIN Rising MA[11:2] Valid Delay from HCLKIN Rising (Read Row Addr) MAA/B[1:0] Valid Delay from HCLKIN Rising (Read Col Addr burst cycles) MA[11:2], MAA/B[1:0] Flow Through Delay from HCLKIN Rising (Read Col Addr leadoff) MA[11:2], MAA/B[1:0] Valid Delay from HCLKIN Rising for a Write Cycle MD[63:0] Setup Time to HCLKIN Rising MD[63:0] Setup Time to HCLKIN Rising for ECC cycles MD[63:0], MPD[7:0] Hold Time from HCLKIN Rising MD[63:0], MPD[7:0] Valid Delay from HCLKIN Rising MPD[7:0] Setup Time to HCLKIN RISING MPD[7:0] Setup Time to HCLKIN Rising for ECC cycles 66 MHz Min 1.5 1.5 1.5 2.0 2.0 2.0 2.0 0 11.0 4.0 2.0 0 11.0 8.0 0 pF Max 6.0 6.0 7.0 9.0 7.0 8.0 10.0 Fig. 3 3 3 3 3 6 3 Notes 0 pf 0 pf 0 pf 0 pf 0 pf 0 pF 0 pF
Table 7. PCI Clock Timing; 66 MHz (82439HX) Functional Operating Range (VDD = 5 V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C) Symbol t70 t71 t72 t73 Parameter PCLKIN High Time PCLKIN Low Time PCLKIN Rise Time PCLKIN Fall Time 66 MHz Min 12.0 12.0 3.0 3.0 Max Figure 1 1 1 1 Notes
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82439HX (TXC) Timing Specification
Table 8. PCI Interface Timing; 66 MHz (82439HX) Functional Operating Range (VDD = 5 V 5%, VDD3 = 3.135 V to 3.6 V; TCASE = 0C to +85C) Symbol t74 t75 t76 t77 Parameter AD[31:0] Valid Delay from PCLKIN Rising AD[31:0] Setup Time to PCLKIN Rising AD[31:0] Hold Time from PCLKIN C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, LOCK#, PAR, DEVSEL# Valid Delay from PCLKIN Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, LOCK#, PAR, DEVSEL# Output Enable Delay from PCLKIN Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, LOCK#, PAR, DEVSEL# Float Delay from PCLKIN Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, LOCK#, PAR, DEVSEL# Setup Time to PCLKIN Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, LOCK#, PAR, DEVSEL# Hold Time from PCLKIN Rising PHLDA# Valid Delay from PCLKIN Rising PHLD# Setup Time to PCLKIN Rising PHLD# Hold Time from PCLKIN Rising GNT[3:0] # Valid Delay from PCLKIN Rising REQ[3:0]# Setup Time to PCLKIN Rising REQ[3:0]# Hold Time from PCLKIN Rising RST# Low Pulse Width 66 MHz Min 2 7 0 2 11 Max 11 Figures 3 4 4 3 Min: 0 pF Max: 50 pF Notes Min: 0 pF Max: 50 pF
t78
2
8
t79
2
28
5
t80
7
4
t81
0
4
t82 t83 t84 t85 t86 t87 t88
2 12 0 2 12 0 1 ms
9.0
3 4 4
Min: 0 pF Max: 50 pF
9.0
3 4 4 7
Min: 0 pF Max: 50 pF
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82439HX (TXC) Timing Specification
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1.5
82439HX System Controller (TXC) Timing Diagrams
Period High Time
2.0V HCLKIN PCLKIN Fall Time 0.8V
2.0V Rise Time 0.8V
Low Time
clocktm.drw
Figure 1. Clock Timing
Input
VT Propagation Delay
Output
VT
prop_del.drw
Figure 2. Propagation Delay
Clock
1.5V Valid Delay
Output
VT Valid Delay
Output
VT
val_del.drw
Figure 3. Valid Delay From Rising Clock Edge
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Clock Setup Time 1.5V
82439HX (TXC) Timing Specification
Hold Time
Input
VT
VT
s ethold.drw
Figure 4. Setup and Hold Times
Input
VT Float Delay
Output
floatdel.DRW
Figure 5. Float Delay
HCLKIN
ADS#
A[31:3], BE[7:0] t47b t55 MA[11:2], MAA[1:0], MAB[1:0]
flowthru.drw
NOTE:
The flow through delay is for the leadoff cycle during a DRAM access. Figure 6. Flow Through Delay
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82439HX (TXC) Timing Specification
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VT VT
Pulse Width
pulsewid.drw
Figure 7. Pulse Width
Clock
1.5V Output Enable Delay
Output
outendel.drw
Figure 8. Output Enable Delay
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